1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, an apparatus and a method for inspecting and repairing a liquid crystal display device capable of reducing a defective rate and increasing production efficiency and yield of the liquid crystal display device.
2. Description of the Related Art
Generally, liquid crystal displays (LCDs) control an electric field supplied to a liquid crystal cell to thereby control light transmittance of liquid crystal material for displaying a desired picture. The liquid crystal displays are classified into a vertical electric field type and a horizontal electric field type in accordance with a direction of the electric field driving the liquid crystal.
The liquid crystal display of vertical electric field type has a common electrode and a pixel electrode formed on an upper substrate and a lower substrate, respectively, such that a vertical electric field is formed in the liquid crystal cell by a voltage applied to the common electrode and the pixel electrode. The liquid crystal display of vertical electric field type has a higher aperture ratio but a narrower viewing angle.
The liquid crystal display of horizontal electric field type has a common electrode and a pixel electrode formed on a same substrate, such that a horizontal electric field is formed to the liquid crystal cell by a voltage applied to the common electrode and the pixel electrode. The liquid crystal display of horizontal electric field type has a wider viewing angle of about 160°. An example of the liquid crystal display of horizontal electric field type is a liquid crystal display device of in-plane switching (hereinafter referred to as “IPS”) mode.
FIG. 1 is a plan view showing a portion of signal lines and a thin film transistor formed on a lower substrate in a liquid crystal display device of in-plane switching (IPS) mode according to the related art, and FIG. 2 is a sectional view of the lower substrate taken along the lines I-I′ and II-II′ in FIG. 1. In FIGS. 1 and 2, the liquid crystal display device of the IPS mode comprises a gate line 2 and a data line 4 with a gate insulating film 46 therebetween formed on a lower glass substrate 45 in such a manner to intersect each other, a thin film transistor (TFT) 6 formed at each intersection of the gate line 2 and data line 4, a pixel electrode 14 connected to a drain electrode 12 of the TFT 6, a common electrode 18 alternatively arranged with the pixel electrode 14 on an identical plane, a common voltage line 16 commonly connected to a plurality of common electrodes 18, and a storage capacitor 20 to maintain a pixel voltage. The liquid crystal display device further comprises an upper substrate having a color filter (not shown), a black matrix and an upper polarizer formed thereon. In addition, liquid crystal materials are injected between the lower substrate and the upper substrate.
The gate electrode 8 of the TFT 6 is connected to the gate line 2, and a scan pulse is supplied to the gate line 2. In an edge of the gate line 2, a gate pad 24, which is connected to an output terminal for the scan pulse in a gate driving circuit, is linked. A source electrode of the TFT 6 is connected to the data line 4, and a data voltage, that is supplied to the pixel electrode 14 of the liquid crystal cell, is applied to the data line 4. In an edge of the data line 4, a data pad 30, which is connected to an output terminal for data voltage in a data driving circuit (not shown), is linked.
The TFT 6, in response to a scan voltage of the gate line 2, supplies the data voltage to the pixel electrode 14. The TFT 6 comprises a gate electrode 8, a source electrode 10, a drain electrode 12, an active layer 48 for forming a channel between the source electrode 10 and the drain electrode 12, and an ohmic contact layer 50 for making an ohmic contact between the active layer 48 and source/drain electrodes 10 and 12.
The pixel electrode 14 is connected to the drain electrode 12 of the TFT 6 via a first contact hole 13 passing through a passivation film 52. The pixel electrode 14 is connected to the drain electrode 12 at its one side and includes a first horizontal part 14A connected to the drain electrode 12 and formed in parallel with its adjacent gate line 2 and a second horizontal part 14B formed to overlap with the common voltage line 16, and a finger part 14C formed in parallel with the data line between the first and the second horizontal parts 14A and 14B.
The common electrode 18 is extended in parallel with the data line 4 from the common voltage line 16 such that it is alternatively arranged with a finger part 14C of the pixel electrode 14 on an identical plane. The common electrode 18 is separated from the pixel electrode 14 by a predetermined distance.
If the data voltage is supplied to the data line 4, a common voltage is supplies to the common voltage line 16 and the common electrode 18, and the scan voltage is supplied to the gate line 2, then the TFT is turned-on and the data voltage is supplied to the pixel electrode 14 via the source electrode 10 and the drain electrode 12 of the TFT 6. At this time, an electric field is supplied between the pixel electrode 14 and the common electrode 18, the electric field being substantially drawn to a horizontal direction. The liquid crystal molecules, in response to the horizontal electric field, is rotated due to a dielectric anisotropy to thereby modulate light.
The storage capacitor 20 includes a dielectric layer, which has a gate insulating film 46, the active layer 48 and the ohmic contact layer 50, a storage electrode 22 and the common voltage line 16 facing each other with the dielectric layer therebetween, and the pixel electrode 14 connected to the storage electrode 22 via a second contact hole 21 passing through the passivation film 52.
The gate pad 24 includes a lower gate pad electrode 26 formed at the edge of the gate line 2 and an upper gate pad electrode 28 connected to the lower gate pad electrode 26 via a third contact hole 27 passing through the gate insulating film 46 and the passivation film 52.
The data pad 30 includes a lower data pad electrode 32 formed at the edge of the data line 4 and an upper data pad electrode 34 connected to the lower data pad electrode 32 via a fourth contact hole 33 passing through the passivation film 52.
A common pad 36 includes a lower common pad electrode 38 formed at the edge of the common voltage line 16 and an upper common pad electrode 40 connected to the lower common pad electrode 38 via a fifth contact hole 39 passing through the passivation film 52.
FIG. 3 is a flow chart of an inspecting process and a repairing process of the liquid crystal display device of FIGS. 1 and 2 according to the related art. In FIG. 3, at steps S1 and S2, the lower glass substrate 45 is taken from the cassette and is inspected on a short circuit of the gate line 8 and the common electrode 18 thereof using an inspecting jig, as shown in FIG. 4 (to be described later).
At step S3, if the substrate 45 is determined to have a good-quality at the step S2, that is, the lower glass substrate 45 in which the gate line 2 and the common voltage line 16 are not shorted, the substrate 45 is transferred to a next process. On the other hand, at step S6, a defective substrate 45 having a short between adjacent the gate line 2 and the common voltage line 16, as determined at the step S2, is returned to a photo-rework process. The photo-rework process is operated in a photo equipment of a mask process on the defective substrate 45. The photo-rework process includes a photo-resist applying process, an arrangement process of a mask, an exposure process, a development process, and a wet etching process, and is carried out again to pattern the gate line 2, the gate electrode 8, the lower gate pad electrode 26, the common voltage line 16, the common electrode 18 and the lower common pad electrode 38.
Alternatively, at step S5, the defective substrates 45, as determined at the step S2, may be repaired through the processes of a pattern inspecting process to closely inspect the patterns of the gate line 2 and the common voltage line 16 along their patterns through the use of a microscope. In addition, at step S7, a laser repairing process is performed to open a short point determined at the pattern inspecting process of step S5 using a laser beam. The substrate 45 after the pattern inspecting process of step S5 can be returned to the photo-rework process of the step S6.
FIG. 4 is a schematic circuit view representing an inspecting jig. In FIG. 4, a measuring multi-meter 201 is controlled by a personal computer (PC) 202 and a plurality of switches SWs supplying voltages supplied from the measuring multi-meter 201 to probe pins 205. In addition, the inspecting jig further includes a driving circuit board (not shown) for supplying an inspecting voltage to the gate line 2 and the common voltage line 16 via a shorting bar provided on the lower glass substrate 45 (not shown). The switches SWs are formed on a relay matrix board and are connected between output lines 203 of the measuring multi-meter 201 and input lines 206 of the probe pins 205, to thereby switch a signal transmission between the measuring multi-meter 201 and the probe pins 205.
The probe pins 205 are fixed on a probe block 204 that is capable of rising and falling. The controlling PC 202 provides a measured data supplied from the measuring multi-meter 201 to a display device (not shown). Moreover, the controlling PC 202 supplies commands required for the inspection, such as an operator's command, through the use of input devices, for example, a keyboard or a mouse, a switch controlling command for controlling the switches, and a command for rising and falling the probe block 204 supporting the probe pins 205 to the driving circuit board of the inspecting jig.
When the lower glass substrate 45 is loaded in the inspecting jig, a testing voltage, which is supplied from the driving circuit board, is provided to the gate line 2 and the common voltage line 16 via the shorting bar. At this time, the probe pins 205 are connected to the lower gate pad electrode 26 and the lower common pad electrode 38. Then, the switches SWs are turned-on. If it is detected that the gate line 2 and the common voltage line 16 are not shorted, a resistance of the gate line 2 and the common voltage line 16 has a value higher than a predetermined reference value measured by the measuring multi-meter 201. However, if it is detected that the gate line 2 and the common voltage line 16 are shorted, a resistance of the gate line 2 and the common voltage line 16 has a value lower than a predetermined reference value due to a conductive alien substance or a defect of a photolithography process. This is because a current path is not formed between the gate line 2 and the common voltage line 16 that are not shorted, while a current path is formed between the gate line 2 and the common voltage line 15 that are shorted .
In the liquid display device of IPS mode, a distance between the gate line 2 and the adjacent common voltage line 16 is about 3 μm as shown in FIG. 1. Thus, a short between the gate line 2 and the common voltage line 16 frequently occurs in this narrow width. In particular, it has been determined that about 30% of the substrates 45 after undergoing a first mask process have a short defect and are returned to the photo-rework process. Further, because it is difficult to locate the short position rapidly and accurately by the pattern inspecting process, few defective substrates 45 are transferred to the laser repair process. Accordingly, the defective substrates are returned to the photo equipment to repeat the first mask process, thereby delaying the photolithography process and reducing production efficiency. This problem worsens with fabricating substrates having a larger size.